Kerem Camsari's p-bits and the One Million p-bit FPGA Computer
Kerem Camsari’s group at the University of California, Santa Barbara has built a probabilistic computer with one million p-bits by networking 18 FPGAs into a single machine. The preprint, arXiv:2606.25313, was posted on 24 June 2026. Navid Anjum Aadit is the first author and Camsari the corresponding author, with eleven co-authors from UC Santa Barbara, Carnegie Mellon University, King Fahd University of Petroleum and Minerals and Siemens. The machine samples at a measured trillion flips per second, and the boards exchange nothing but 1-bit boundary states.
In short, p-bits are binary units that flip at random with a bias set by their inputs, and a network of them samples an Ising model. The new result is a measured rule for how often the pieces of a split machine must talk to behave as one. That rule has a direct counterpart in a question this site has asked about distributed minds.
What a p-bit is
A p-bit is a binary unit that fluctuates between two states at random. Camsari, Rafatul Faria, Brian Sutton and Supriyo Datta introduced it for invertible logic in Physical Review X in 2017, and Camsari, Sutton and Datta set it out as a general unit in Applied Physics Reviews in 2019. Each p-bit reads a weighted sum of its neighbours, its input h. It then takes the value +1 with probability (1 + tanh(βh)) / 2 and −1 otherwise. A large positive input makes +1 almost certain. An input of zero gives a fair coin.
Coupled p-bits that follow this rule sample the Boltzmann distribution of an Ising model. Low-energy configurations come up more often, and the gain β plays the part of an inverse temperature. That one property serves two kinds of work. Optimization looks for the lowest-energy state, and probabilistic inference needs many samples from the distribution. The 2019 review proposed a magnetic tunnel junction with a low energy barrier as a physical p-bit, driven by thermal noise at room temperature. The chips that Extropic calls thermodynamic sampling units use the same unit, built from standard transistors, as set out in the post on Extropic THRML.
Why graph colouring lets every p-bit update at once
Two coupled p-bits must not update in the same step, or the machine stops sampling the right distribution. A CPU avoids the problem by updating one unit at a time, which is slow. The answer in Aadit, Camsari and co-authors’ 2022 paper in Nature Electronics is to keep the graph sparse and colour it so that no two neighbours share a colour. All p-bits of one colour can then update together, and a full sweep takes as many steps as there are colours.
The 2022 FPGA machine reported a flip rate that grows linearly with the number of p-bits. The authors measured it at up to six orders of magnitude faster than standard Gibbs sampling on a CPU and 5 to 18 times faster than approaches on tensor and graphics processors. The same paper suggested the design could reach “1,000,000 or more p-bits” with analogue silicon or nanodevices. The 2026 machine reached that number with digital FPGAs.
The Thermodynamic Computing hub runs the same scheme in the browser. Its Ising view updates a lattice in two colours, so the reader can watch the parallel step that the FPGA does in one clock cycle.
The one million p-bit machine
One FPGA has a fixed amount of logic and on-chip memory, and an Ising machine needs both for its p-bits and its coupling weights. The 2026 design cuts one large sparse graph into partitions with a balanced min-cut, places one partition on each device, and keeps every weight in local memory. Each weight on a cut edge is stored on both sides, so only the 1-bit state of a boundary p-bit ever crosses between boards. The authors built two platforms.
| DSIM-1 | DSIM-2 | |
|---|---|---|
| Devices | 6 FPGAs in a chain over FMC links | 18 AMD VP1902 FPGAs on a Siemens Veloce proFPGA CS platform |
| Clocks | Independent local clock per board | One shared master clock |
| Largest test | 50,653 p-bits (a 37 × 37 × 37 lattice) | 1,000,000 p-bits (100 × 100 × 100), 72 sub-partitions |
| Measured flip rate | 5.1 × 10⁹ per second at 0.10 MHz, 2.53 × 10¹² at 50 MHz | 10¹² per second at 1 MHz, 3 × 10¹² at 3 MHz |
| Power, whole platform | 150 to 180 W | 1.4 to 1.6 kW |
All figures are the authors’ own measurements. The test problem is the three-dimensional Edwards-Anderson spin glass, a standard hard benchmark. At one million p-bits and 1 MHz, the residual energy fell at the same rate as on a monolithic GPU reference, with exponents of 0.2820 and 0.2836. Above 3 MHz the 18 boards lost read and write synchronization.
The machine also solved three problems on other graphs. On the G81 Max-Cut instance, a 20,000-node grid, it reached the certified optimum cut of 14,060. It solved planted instances on the Pegasus and Zephyr graphs used by D-Wave quantum annealers, with 39,040 and 80,800 p-bits. A random 3SAT instance with 13,042 variables, encoded in 250,011 p-bits, reached 55,416 of 55,558 clauses satisfied.
The timing ratio that decides whether the pieces act as one
The central result concerns stale information. A p-bit next to a cut reads neighbours on another board, and their states are only as current as the last exchange. The authors show that one number, η, the boundary-exchange frequency divided by the local p-bit update frequency, predicts the behaviour. Above a threshold that depends on the graph, the split machine samples as well as an unsplit one. Below it, the residual energy still falls as a power law, but with a smaller exponent.
At one million p-bits, raising the clock from 1 MHz to 3 MHz lowered η and the exponent fell from 0.2820 to 0.2565. The machine produced more flips per second, each based on staler boundary data. It reached an easy target 2.82 times faster but lost its advantage for targets below a residual energy of about 0.004. A cluster mean-field model, in which clusters run exact local dynamics against frozen outside fields, reproduces the same reduction, and the authors present the tradeoff as a general property of partitioned stochastic dynamics.
The same question for a distributed mind
This site has asked the same question for consciousness. Wolf Singer’s temporal binding argument sets a 25 ms window, one gamma cycle, within which distributed neural assemblies must synchronize to bind features into one percept. Spread the parts of a system so far apart that signals take longer than that, and on Singer’s account the parts can no longer form one conscious state. That is a ratio of exchange delay to the system’s own update period, the same form as η.
The two cases differ in what the ratio protects. Singer’s window protects phase coherence in an oscillating network. Camsari’s η protects the accuracy of a sampler. The p-bit result adds one thing the binding argument does not have, a measurement. In the p-bit machine, crossing the threshold did not cause a sudden failure. Quality degraded by a measurable amount, the exponent, and the authors could trade it against speed. If the binding requirement behaves the same way, a distributed mind would lose coherence by degree as its parts drift apart in time, without a sharp cliff at 25 ms. The analogy is this site’s, and nothing in the paper tests it. It does turn a verbal threshold into a quantity that a model could estimate.
Comparison to The Consciousness AI
The project runs p-bits only in software. Its emulator, models/thermodynamic/p_bit_emulator.py, uses the update rule of the 2017 Physical Review X paper and the chromatic block Gibbs scheme described above. It rejects any colouring that would put two coupled p-bits in the same step. A stand-in driver runs the same emulator behind the interface a hardware driver would use. The repository has no driver for any FPGA board and no partitioned sampler, so the timing ratio has no counterpart in the project’s code.
The project’s test of whether its representations survive a noisy p-bit channel is published in docs/results/thermodynamic_survival_2026_10.md. A known stimulus is still told apart from the others after the channel. Shape on an unseen stimulus is at chance with or without the channel, and Gaussian sensory noise of standard deviation 8 drops the shape decode to chance before any channel is applied. That is a software result and gives no hardware number.
Running p-bits on a desk
The machines in the paper use AMD VP1902 devices, the largest FPGAs available, on a commercial prototyping platform. The method itself is not tied to that scale. A sparse graph, a colouring and one random number source per p-bit fit on a small board, and the paper’s own p-bits draw their randomness from on-chip linear-feedback shift registers. The thermodynamic computing hardware guide lists FPGA boards sold today, such as the Sipeed Tang Nano 9K and 20K, with the logic size of each. None of them reaches a million p-bits, and this project has no gateware for any of them.
What is known and what is not
Known on 30 October 2026. Kerem Camsari’s group has run one million p-bits as one Ising machine across 18 FPGAs at a measured trillion flips per second. At its safe clock the split machine matched a GPU reference on a hard spin glass. One timing ratio predicts when the split machine matches an unsplit one, and below the threshold the loss is graded and measurable. The work is a preprint and has not been peer reviewed.
Not known. Whether the same design rule holds for p-bits made from noisy physical devices instead of digital logic. Whether a p-bit machine of any size can run the parts of an architecture that carry content, which is the substrate independence test this project needs. Whether binding in a brain degrades by degree as the η analogy suggests. The paper answers a hardware question precisely and leaves the consciousness question open. The broader effort to agree on criteria for consciousness in any system is reviewed in the race to define AI consciousness.
Researchers covered here
- Kerem CamsariDepartment of Electrical and Computer Engineering, University of California, Santa BarbaraThe p-bit, a binary unit that fluctuates at random under the control of its inputs, and probabilistic computers built from p-bits on FPGAs, including a networked machine with one million p-bits (arXiv 2606.25313, 2026)
- Navid Anjum AaditDepartment of Electrical Engineering, Stanford University (present address); previously University of California, Santa BarbaraFirst author of the sparse Ising machine on FPGAs (Nature Electronics, 2022) and of the programmable probabilistic computer with one million p-bits (arXiv 2606.25313, 2026)
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Supriyo DattaElmore Family School of Electrical and Computer Engineering, Purdue UniversityQuantum transport theory of nanoscale devices, the Datta-Das spin transistor proposal (1990), and co-authorship of the p-bit framework for probabilistic computing (2017, 2019)