Kerem Camsari and Corentin Delacour Map Probabilistic Algorithms and PAOA for Ising Machines
What algorithms turn a physical array of noisy, fluctuating probabilistic bits (p-bits) into a programmable engine capable of both hard combinatorial optimization and energy-based generative AI? In their review paper Probabilistic Algorithms for Ising Machines from Optimization to Generative AI (arXiv:2610.03972 / Nature Reviews Electrical Engineering), University of California, Santa Barbara researchers Corentin Delacour, Xiuqi Zhang, Abdelrahman S. Abdelrahman, Saleh Bunaiyan, Kyle Lee, Shuvro Chowdhury, and Kerem Y. Camsari map the co-evolution of stochastic hardware and probabilistic algorithms, centering on the Probabilistic Approximate Optimization Algorithm (PAOA).
For the Thermodynamic Computing hub and our ongoing coverage of how scientists define and test consciousness across physical substrates, Delacour and Camsari’s synthesis bridges the gap between raw device physics and trainable circuit intelligence. While Kerem Camsari’s one-million p-bit distributed FPGA computer proved that chromatic Gibbs sampling can exceed a trillion flips per second across networked chips, and Isaac Chuang and Extropic’s Denoising Thermodynamic Computer Architecture (DTCA) proposed sub-threshold CMOS denoising pipelines, hardware speed means little if the system traps in local energy minima. Delacour and Camsari show how variational schedules, parallel tempering, and cluster mean-field updates expand the computational capacity of physical Ising machines.
The Algorithmic Stack for Programmable Ising Machines
An Ising machine represents computational states as binary spins $s_i \in {-1, +1}$ coupled by an interaction matrix $J_{ij}$ and local biases $h_i$, evolving toward the Boltzmann distribution of the Ising energy function $E(s) = -\sum_{i<j} J_{ij} s_i s_j - \sum_i h_i s_i$. When implemented with probabilistic bits (p-bits) built from stochastic magnetic tunnel junctions (sMTJs), CMOS ring-oscillator true random number generators, or FPGA lookup tables, each p-bit updates according to $m_i(t+1) = \text{sgn}\big(\tanh(\beta I_i(t)) - r_u\big)$, where $\beta$ is the inverse pseudo-temperature and $r_u \in [-1, 1]$ is uniform thermal or hardware noise.
Delacour and Camsari organize the algorithmic stack for these physical samplers into four progressive families.
- Simulated annealing and chromatic block Gibbs sampling sweep a single global inverse temperature $\beta(t)$ upward on sparse bipartite or King’s-graph lattices. By coloring the graph so no two adjacent p-bits share a color, hardware clocks update entire color blocks simultaneously in a single nanosecond cycle without race conditions.
- Parallel tempering (replica exchange) runs $R$ coupled hardware replicas of the same Ising graph at stepped inverse temperatures $\beta_1 < \beta_2 < \dots < \beta_R$, periodically swapping replica states via a Metropolis-Hastings acceptance criterion so high-temperature thermal exploration feeds low-temperature ground-state refinement.
- Cluster mean-field and Swendsen-Wang non-local updates overcome critical slowing down near spin-glass phase transitions by grouping strongly correlated p-bits into dynamic clusters and flipping them coherently, bypassing energy barriers that trap single-spin Glauber or Metropolis updates.
- The Probabilistic Approximate Optimization Algorithm (PAOA) replaces hand-tuned annealing schedules with a variational quantum-inspired circuit executed on classical p-bits.
| Algorithmic Family | Temperature / Coupling Control | Escape Mechanism from Local Minima | Hardware Mapping Overhead | Primary Workload |
|---|---|---|---|---|
| Chromatic Simulated Annealing | Single global scalar $\beta(t)$ ramp | Thermal single-spin flips only | Minimal (single sparse lattice on FPGA/sMTJ) | Fast heuristic Max-Cut & SAT |
| Parallel Tempering (Replica Exchange) | $R$ fixed temperatures $\beta_1 \dots \beta_R$ | Non-local state swaps between hot and cold replicas | $R\times$ lattice area or time-multiplexed replicas | Rugged 3D spin glasses & integer factorization |
| Cluster / Swendsen-Wang Updates | Bond-activation probabilities $p_{ij} = 1 - e^{-2\beta J_{ij}}$ | Collective multi-spin cluster flips | Dynamic connected-component routing logic | Critical phase transitions & lattice sampling |
| PAOA (Delacour & Camsari 2026) | $2p$ trainable layer parameters $(\boldsymbol{\gamma}, \boldsymbol{\beta})$ | Variational schedule tailored to problem topology | Time-multiplexed depth $p$ on existing p-bit arrays | Combinatorial optimization & Boltzmann generative AI |
How the Probabilistic Approximate Optimization Algorithm (PAOA) Works
Inspired by Edward Farhi’s Quantum Approximate Optimization Algorithm (QAOA), which alternates between a problem Hamiltonian and a transverse-field mixer unitary on a quantum processor, PAOA formulates a purely classical variational Monte Carlo ansatz native to probabilistic hardware.
Instead of applying a uniform annealing ramp to every synapse in the network, a PAOA circuit of depth $p$ divides the physical sampling run into $p$ discrete markovian layers. Each layer alternates between two parameterized stochastic transition kernels. First, a cost-layer transition evolves the p-bits under the problem couplings scaled by a trainable parameter $\gamma_k$. Second, a mixer-layer transition modulates the thermal fluctuation rates or auxiliary mixing couplings via a trainable parameter $\beta_k$.
Because the p-bit hardware generates thousands of independent trajectories per millisecond, a classical outer-loop optimizer (such as simultaneous perturbation stochastic approximation or natural gradient descent) evaluates the expected energy $\langle E \rangle$ directly from hardware readouts and updates the $2p$ parameters $(\gamma_1 \dots \gamma_p, \beta_1 \dots \beta_p)$. Delacour and Camsari demonstrate that PAOA discovers non-monotonic temperature and coupling trajectories that outperform standard simulated annealing at equal flip budgets, while requiring no quantum coherence or cryogenic cooling. Readers who want to run chromatic Gibbs sampling and PAOA-style schedules on accessible hardware can inspect the FPGA boards and physical noise sources in our thermodynamic computing hardware guide, which pairs directly with Normal Computing’s CN101 thermodynamic linear algebra architecture.
Connection to Consciousness Theory and Generative World Models
Why does a review of Ising machine algorithms bear on the scientific study of consciousness? In both Karl Friston’s Active Inference / Free Energy Principle and Giulio Tononi’s Integrated Information Theory (IIT), a conscious or world-modeling substrate must solve a formidable physical integration problem. It must settle into a globally coherent perceptual interpretation across millions of recurrently coupled units within tens of milliseconds, without getting trapped in fragmented local attractors.
Standard digital simulations of Boltzmann machines and energy-based world models fail to scale because single-spin Markov Chain Monte Carlo (MCMC) mixes too slowly across high-dimensional energy surfaces. Delacour and Camsari’s synthesis of parallel tempering, cluster updates, and variational PAOA schedules shows how physical stochastic substrates overcome that mixing wall. When thermal noise drives parallel p-bit flips across a sparse recurrent graph, variational control of the coupling gains ($\gamma_k$) and noise precision ($\beta_k$) acts as an exact physical analog of thalamic precision weighting and neuromodulatory gain control in the biological brain.
In biological cortex, noradrenergic and cholinergic arousal systems dynamically flatten or sharpen the neural energy surface so cortical assemblies can escape stale perceptual interpretations and ignite a new global state. PAOA formalizes that same energy-shaping operation in silicon. Needless to say, no FPGA Ising machine or sMTJ array running PAOA is conscious; rather, these variational stochastic algorithms demonstrate how substrate-independent physical hardware can execute fast, globally integrated energy minimization without a von Neumann bottleneck.
Comparison to The Consciousness AI
In The Consciousness AI, our Thermodynamic Computing hub includes interactive browser emulations of chromatic block Gibbs sampling on Ising lattices, p-bit activation curves, and continuous-time phase relaxation. All thermodynamic models in our repository currently run in software emulation, and as recorded in our November 2026 research map, heavy thermodynamic training runs are paused while workspace-to-behavior causal links are diagnosed.
Delacour and Camsari’s PAOA framework highlights a clear algorithmic upgrade for energy-based workspace modules. Rather than tuning a single static temperature parameter when sampling candidate workspace broadcasts, a small number of variational schedule parameters $(\boldsymbol{\gamma}, \boldsymbol{\beta})$ can be meta-learned so the network rapidly mixes during ambiguous sensory input and locks into a low-entropy broadcast state within a fixed step budget.
Hardware Limits and Open Challenges
Delacour and Camsari identify three concrete engineering hurdles that govern the transition from optimization benchmarks to large-scale generative AI. First, embedding dense or irregular problem graphs onto sparse 2D hardware lattices via minor-embedding introduces chains of auxiliary p-bits whose internal ferromagnetic couplings can dominate the energy spectrum and freeze dynamics. Second, while FPGA prototypes provide full digital reconfigurability for multi-bit synaptic weights, scaling monolithic sMTJ+CMOS chips beyond millions of p-bits requires low-power on-chip weight storage that avoids SRAM area bloat. Third, training deep energy-based generative models via contrastive divergence on noisy hardware requires matching the inference-phase PAOA schedule to the equilibrium gradients needed for stable weight updates.
Researchers covered here
- Corentin DelacourDepartment of Electrical and Computer Engineering, University of California, Santa BarbaraProbabilistic Approximate Optimization Algorithm (PAOA), Ising machine algorithms, coupled oscillator and p-bit circuit design
- Kerem CamsariDepartment of Electrical and Computer Engineering, University of California, Santa BarbaraThe p-bit, a binary unit that fluctuates at random under the control of its inputs, and probabilistic computers built from p-bits on FPGAs, including a networked machine with one million p-bits (arXiv 2606.25313, 2026)