Yang, Grimaldi and Finocchio Build a 250-MTJ Probabilistic Ising Machine
Can nanoscale magnetic junctions driven by room-temperature thermal and spin-torque fluctuations scale beyond toy eight-bit demonstrations to solve hard combinatorial optimization problems at high speed? In their 2026 Nature Communications paper 250 magnetic tunnel junctions-based probabilistic Ising machine (doi:10.1038/s41467-026-72020-8, arXiv:2506.14590), Shuhan Yang, Andrea Grimaldi, Youwei Bao, Eleonora Raimondo, Jia Si, Giovanni Finocchio, and Hyunsoo Yang from the National University of Singapore and the University of Messina report an experimental probabilistic Ising machine (PIM) built from 250 spin-transfer torque magnetic tunnel junctions (STT-MTJs) interfaced with an FPGA controller.
For the Thermodynamic Computing hub and our ongoing coverage of how scientists define and test consciousness across physical substrates, this demonstration supplies the missing spintronic hardware bridge between digital FPGA emulations and true physical noise samplers. While Kerem Camsari’s one-million p-bit computer relied on digital pseudorandom linear-feedback shift registers (LFSRs) inside AMD FPGAs, and our analysis of Johnson-Nyquist thermal noise and USB true random number generators showed that external USB entropy sources are tens of millions of times too slow for large lattices, Yang, Grimaldi, Finocchio, and Yang generate true physical randomness directly inside 250 nanoscale magnetic tunnel junctions on the board.
How Spin-Transfer Torque MTJs Act as Physical p-bits
A magnetic tunnel junction consists of two ferromagnetic layers separated by an ultrathin magnesium oxide (MgO) insulating barrier only a few atomic planes thick. The magnetization of the reference layer is pinned in a fixed direction, while the magnetization of the free layer can flip between two states, namely parallel (P, low electrical resistance via tunneling magnetoresistance, representing Ising spin $s_i = -1$) and antiparallel (AP, high electrical resistance, representing $s_i = +1$).
In conventional magnetoresistive random-access memory (MRAM), the energy barrier between the parallel and antiparallel states is engineered high ($E_b \approx 40\text{ to }60\, k_B T$) so bits retain data for ten years, whereas in early stochastic MTJs (such as the 8-p-bit integer factoring circuit demonstrated by Borders, Camsari, and Datta in 2019), the barrier was lowered near $k_B T$ so ambient room-temperature heat flipped the magnet continuously.
Yang, Grimaldi, Finocchio, and Hyunsoo Yang operate their 250 STT-MTJ array in a current-tunable stochastic switching regime. By applying controlled spin-transfer torque current pulses through each junction in the presence of room-temperature thermal agitation, the probability of switching from parallel to antiparallel follows a tunable sigmoidal activation curve,
\[P(s_i = +1) = \frac{1}{1 + \exp(-\beta I_i)}\]where $I_i = \sum_j J_{ij} s_j + h_i$ is the local synaptic field computed from neighboring spins by the companion FPGA and $\beta$ is the effective inverse temperature. This hybrid architecture delivers three concrete hardware capabilities.
- Each of the 250 STT-MTJ devices functions as a tunable spintronic true random number generator (TRNG) whose entropy comes from quantum-mechanical electron tunneling and thermal magnetization fluctuations rather than deterministic digital logic.
- Because the FPGA computes the coupling matrix $J_{ij}$ digitally and feeds biased pulse trains back to the 250 physical junctions, the machine supports arbitrary, fully connected Ising graph topologies as well as sparse benchmark lattices without rewiring physical metal traces.
- Short-pulse switching measurements down to the nanosecond regime confirm that STT-MTJ p-bit arrays can achieve orders-of-magnitude gains in sampling speed and energy efficiency over graphics processing units (GPUs) once integrated directly with CMOS peripheral drivers.
| Probabilistic Hardware Platform | Randomness / p-bit Mechanism | Physical Device Count | Graph Connectivity | Key Algorithmic & Performance Result |
|---|---|---|---|---|
| Borders, Camsari & Datta (2019) | Low-barrier thermal sMTJ | 8 physical MTJ p-bits | All-to-all (small scale) | Factored integers up to 945 at room temperature |
| Aadit & Camsari DSIM-2 (2026) | Digital LFSR pseudorandom on FPGA | 1,000,000 digital p-bits (18 FPGAs) | Sparse colored lattices (3D spin glass) | $10^{12}$ flips/sec; boundary exchange ratio $\eta$ law |
| USB Hardware TRNGs (InfNoise / OneRNG) | Resistor Johnson-Nyquist / diode avalanche | 1–2 discrete noise channels | Host software bound | ~259–300 kbit/s (too slow for high-speed Ising arrays) |
| Yang, Grimaldi, Finocchio & Yang (2026) | Current-driven STT-MTJ spintronic TRNGs + FPGA | 250 physical STT-MTJs | Fully connected & sparse graphs | 10$\times$ cluster parallel speedup; 20$\times$ SQA solution quality |
10x Cluster Parallel Speedup and 20x Simulated Quantum Annealing Quality
A longstanding criticism of physical nanodevice Ising machines is that device-to-device fabrication variations (slight differences in tunnel barrier thickness, coercive field, or resistance-area product across 250 junctions) distort the Boltzmann distribution and trap standard simulated annealing in poor local minima. Connecting directly to the algorithmic taxonomy reviewed in Corentin Delacour and Kerem Camsari’s 2026 study of probabilistic algorithms and PAOA for Ising machines, Yang, Grimaldi, Finocchio, and Yang overcome both the serial update bottleneck and device variability through two algorithmic innovations executed on the 250-MTJ hardware.
First, for sparsely connected combinatorial optimization graphs, standard Gibbs sampling updates one spin at a time to prevent neighboring spins from flipping simultaneously on stale information. The authors implement a cluster parallel update technique that partitions independent spin neighborhoods and updates them in parallel across the 250 STT-MTJ channels, achieving a 10-fold acceleration in time-to-solution with zero hardware modifications.
Second, the team maps Simulated Quantum Annealing (SQA) onto the probabilistic spintronic array. Via the Suzuki-Trotter decomposition, a $D$-dimensional quantum Ising Hamiltonian in a transverse magnetic field $\Gamma(t)$ maps onto a $(D+1)$-dimensional classical Ising system consisting of multiple coupled “Trotter replicas” running in parallel across the MTJ p-bits. As the transverse field schedule $\Gamma(t)$ sweeps down, inter-replica ferromagnetic couplings allow the system to tunnel through narrow, high energy barriers rather than climbing over them thermally. On the 250-MTJ machine, SQA boosts ground-state solution quality by 20 times compared to conventional simulated annealing, while simultaneously averaging out static device-to-device threshold variations across the coupled replicas.
Why Physical Spintronic Stochasticity Bears on the Consciousness Debate
How does a 250-MTJ spintronic Ising machine bear on the science of consciousness? Under functionalist emergentism and thermodynamic accounts of neural computation, a central open question is whether the physical origin of noise and state transitions changes the macroscopic causal capabilities of a recurrent network.
In biological brains, ion-channel gating and synaptic vesicle release are governed by genuine kT-scale thermal fluctuations, allowing neural assemblies to sample probabilistic perceptual interpretations rapidly at roughly 20 watts of total power. Digital simulations on GPUs or FPGAs approximate those dynamics using deterministic pseudorandom formulas (Philox or LFSRs) at a massive energy multiplier. Meanwhile, critics of computational functionalism, including Anil Seth, Ned Block, and Giulio Tononi in their October 2026 Nature comment, argue that digital software decoupled from physical substrate dynamics lacks intrinsic causal integration.
Spintronic p-bit arrays sit directly on that boundary. In the 250-MTJ machine, each binary state transition is a real, physically irreversible thermodynamic event in a magnetic nanodevice, and the Trotterized SQA coupling binds multiple physical subsections into a coordinated energy-minimizing trajectory. Needless to say, a 250-MTJ combinatorial optimizer is not conscious and has no sensory or homeostatic world model. What it proves is an essential substrate engineering fact, showing that room-temperature spintronic devices can supply high-throughput physical stochasticity and 20-fold improved global energy convergence while tolerating the device-to-device variability that characterizes both nanoscale hardware and biological wetware. Readers who want to compare commercial and open-source FPGA boards and physical noise generators can consult our thermodynamic computing hardware guide.
Comparison to The Consciousness AI
In The Consciousness AI, our Thermodynamic Computing hub and software p-bit emulator (models/thermodynamic/p_bit_emulator.py) model chromatic block Gibbs sampling and Ising energy relaxation using seeded PyTorch generators. Our project does not fabricate or operate spintronic MTJ hardware, and all thermodynamic experiments in the repository are software emulations.
Two findings from Yang, Grimaldi, Finocchio, and Yang’s 250-MTJ paper directly inform our software-to-hardware roadmap. First, their demonstration that Simulated Quantum Annealing (SQA) via coupled Trotter replicas naturally suppresses static device-to-device variability provides a concrete architectural mechanism for keeping a workspace sampler coherent when running on imperfect physical devices. Second, their 10-fold cluster parallel update speedup complements the chromatic coloring rules implemented in our emulator, showing how sparse connectivity graphs can maximize parallel flips per clock cycle.
Scaling From 250 MTJs to Monolithic Spintronic Arrays
While 250 STT-MTJs represent a more than 30-fold scale-up over early 8-MTJ demonstrations, reaching the 100,000 to 1,000,000 p-bit regime currently occupied by multi-FPGA digital clusters requires moving from discrete board-level FPGA-to-MTJ wiring to monolithic CMOS-integrated spintronic chips (1T-1MTJ crossbar arrays). Solving the on-chip routing of multi-bit synaptic weights $J_{ij}$ without drowning the nanoscale magnetic junctions in SRAM peripheral area remains the primary circuit-design frontier for spintronic thermodynamic computing.
Researchers covered here
- Shuhan YangDepartment of Electrical and Computer Engineering, National University of Singapore250-MTJ Probabilistic Ising Machine, spin-transfer torque magnetic tunnel junction p-bits, cluster parallel annealing
- Andrea GrimaldiDepartment of Mathematical and Computer Sciences, Physical Sciences and Earth Sciences, University of MessinaSpintronic probabilistic computing, 250-MTJ Probabilistic Ising Machine, simulated quantum annealing on p-bits
- Giovanni FinocchioDepartment of Mathematical and Computer Sciences, Physical Sciences and Earth Sciences, University of MessinaSpintronic neuromorphic and probabilistic computing, 250-MTJ Probabilistic Ising Machine, micromagnetic solver development
- Hyunsoo YangDepartment of Electrical and Computer Engineering, National University of SingaporeSpintronics and magnetic tunnel junction fabrication, 250-MTJ Probabilistic Ising Machine, spin-orbit torque devices